W4: For variability, shelf-life (oxidation) and constant deposit rate are key. Test patterns on silicon for after-the-fact. Resistance testing is useful/common. Laser cutter can oblate/cut sections and rely on a redundant section. Acid etching may be possible. Heating and removal may be possible. "MISFET" metal-insulator semiconductor field effect transistor. Schottky diode--metal (Schottky)-semiconductor-metal (ohmic) sandwich. Work function of metal versus electron affinity in semiconductors essentially the same. Bonds covalent. Electrons move into metal and becomes less [pn]-type. Barrier forms where electrons left and voltage happens. Difference in other direction causes flow of electrons and ohmic contact. Can either vary metal or doping. Lookup leaky / Schottky diodes versus regular pn-junction. Schottky transistors also possible. In the end we want CMOS to save material. NAND CMOS is 4 transistors. TTL has 3 transistors and 4 resistors. Also, CMOS has much better fanout. Look into verilog/VHDL output. For Thursday: carbon. Keep thinking about deposition method. Get transparencies from John.